Substrate processing combining advanced lithographic processing and thin film deposition techniques enables fabrication and integration of device structures having dimensions ranging from 10s of nanometers to 10s of centimeters. Such state of the art material processing methods are generally compatible with a range of substrate and deposition materials, including high quality dielectric, semiconducting, conducting and biological materials. Given the degree of precision and versatility provided by these methods, substrate patterning techniques provide a robust fabrication platform for accessing a wide range of useful functional devices. For example, advanced lithographic processing and thin film deposition techniques play a central role in most semiconductor based technologies including, but not limited to, the manufacture of dense integrated circuits, memory devices, and microelectronic display systems. Furthermore, advanced lithographic processing and thin film deposition techniques also provide the primary fabrication platform for making micro- and nano-electromechanical (MEMS & NEMS) and micro- and nano-fluidic systems supporting a range of applications, including sensing.
Recent developments in lithographic processing, including deep ultraviolet photolithography, electron beam writing and X-ray lithography methods, continue to extend the applicability of these techniques for generating patterns of smaller and smaller structures on substrates. Advances in lithographic processing and etching techniques, for example, make it possible to generate high aspect ratio recessed features (e.g., aspect ratio>10:1 depth:width) having well defined nanometer and micron sized dimensions. High aspect ratio structures having these dimensions have potential to support densely packed device elements for future generations of microelectronic and nanoelectronic systems, such as diffusion barriers, insulator layers, and electrical contacts and interconnects. As target device dimensions continue to be reduced with the evolution of advanced lithography techniques, significant technical challenges are presented for conformally filling or coating such high aspect ratio nanometer and micron sized structures with functional materials. These challenges constitute a barrier to achieving the desired reduction of device dimensions in ultra-large scale integrated circuit (ULSI) architecture and the multilevel metallization therein.
To fabricate certain device components, a selected material or combination of materials is deposited onto recessed features, such as trenches or vias, patterned into a substrate surface that spatially defines and integrates the elements of the device. Deposition is commonly accomplished by exposure of the feature to a precursor gas or combination of precursor gases that condenses on, or reacts on or with, surfaces of the feature, to generate deposited layers that coat and/or fill the recessed feature with a functional material having selected properties. Important to providing device components exhibiting good electrical, mechanical, optical and/or other properties, is the ability to provide a highly smooth thin film structure, for example, a smooth film filling or coating recessed features in a continuous and conformal manner. For example, deposition methods are needed for some device applications that form a smooth thin film layer in or on the feature without voids or gaps in the bulk of the deposited material. Voids and gaps, such as pinholes, are undesirable because they affect the electronic and chemical properties of the deposited layer, such as inductance, resistivity and/or capacitance, thereby, potentially degrading overall device performance and undermining device uniformity. Further, voids and gaps in the bulk of the deposit or between the deposit and surfaces of the recessed feature also compromise overall mechanical integrity of the processed structure and may give rise to device failure. As an example, there is currently a need for processing techniques for making thin diffusion barriers without any pinholes or other gaps, as such device structures may fail if there is even a single pinhole allowing incompatible materials to penetrate—such as Cu in dielectric layers.
To address these challenges a number of processing strategies have been developed for coating or filling high aspect ratio recessed features for fabrication of a microelectronic device. While at least in part addressing some of the problems with processing high aspect ratio features, these techniques are not compatible with all types of deposition materials, substrates and recessed feature geometries. In addition, each technique presents its own set of limitations that impedes adoption and implementation.
Physical vapor deposition (PVD) encompasses a gamut of techniques including evaporation, sputtering and variants thereof. Due to the near-unity net sticking coefficient of the arriving flux in most PVD coating applications, the ability of PVD processes to coat high aspect ratio features uniformly is severely limited. Modified PVD processes, however, such as collimated sputtering and ionized PVD have been demonstrated to provide some limited success in coating and filling moderate aspect ratio (≦5:1) features. (See, S. M. Rossnagel, J. Vac. Sci. Technol. B 16 (1998) 2585).
Conventional thermal and plasma based chemical vapor deposition (CVD) processes typically perform well for moderate to low aspect ratio (≦5:1) structures. The success of these processes for coating higher aspect ratio features is largely dependent on operating in a regime in which the reactive species has a relatively low net sticking coefficient with respect to accommodation on the feature. (See, M. M. Islamraja, M. A. Cappelli, J. P. McVittie, K. C. Saraswat, J. Appl. Phys. 70 (1991) 7137; and H. C. Wulu, K. C. Saraswat, J. P. Mcvittie, J. Electrochem. Soc. 138 (1991) 1831.)
A modified approach, high density plasma (HDP) CVD and variants, employs physical erosion (sputtering) of the deposited material by high energy ions to remove material from the exposed surfaces, including the trench opening. (See, S. V. Nguyen, IBM J. Res. Dev. 43 (1999) 109; D. R. Cote, S. V. Nguyen, A. K. Stamper, D. S. Armbrust, D. Tobben, R. A. Conti, G. Y. Lee, IBM J. Res. Dev. 43 (1999) 5; and K. Takenaka, M. Kita, T. Kinoshita, K. Koga, M. Shirantani, Y. Watanabe, J. Vac. Sci. Technol. A 22 (2004), 1903). The flux of high energy ions does not impinge on the lower side walls of the trench; hence the film grows at a greater net rate in lower regions of the trench. Film and substrate damage from high energy ions, however, can be a severe limitation in this process.
Another approach is selective deposition by CVD, which is based on the inability of the precursor to nucleate a film on one substrate material compared to another. This approach has been utilized to selectively grow films on recesses in a substrate. The CVD of tungsten (W) and of group III-V semiconductors from their halogen based precursors are examples in which films nucleate on a semiconductor substrate but not on a mask material such as SiO2. (See, T. F. Kuech, M. S. Goorsky, M. A. Tischler, A. Palevski, P. Solomon, R. Potemski, C. S. Tsai, J. A. Lebens, K. J. Vahala, J. Cryst. Growth 107 (1991) 116; and K. C. Saraswat, S. Swirhun, J. P. McVittie, J. Electrochem. Soc. 131 (1984) C86). A nucleation layer at the bottom of a trench or, via can afford a bottom-up fill as demonstrated for Al-CVD. (See, L. Y. Chen, T. Guo, R. C. Mosley, F. Chen, Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug, U.S. Pat. No. 6,537,905, Applied Materials Inc., 2003). Successful implementation of such approaches, however, depends on the ability to establish high density nucleation conditions necessary for generating a smooth thin film layer. Disadvantages of these techniques include the need for intermediate photolithographic steps to define a mask layer, and the need for mechanical polishing to remove unwanted seed layer.
Atomic Layer Deposition (ALD) is a technique with proven capability to coat aspect ratios exceeding 100:1. (See, R. G. Gordon, Abstr. Pap. Am. Chem. Soc. 227 (2004) U553; J. E. Crowell, J. Vac. Sci. Technol. A 21 (2003) S88; H. Kim, J. Vac. Sci. Technol. B 21 (2003) 2231; B. S. Lim, A. Rahtu, R. G. Gordon, Nat. Mater. 2 (2003) 749). The ALD process works by sequential exposure of the substrate to two or more different reactant gases (e.g., co-reactants) under the special condition that the surface reactions during each exposure are self-limiting. The film typically grows at a very slow rate (e.g. a fraction of a monolayer per cycle), and, therefore, the cycle time is limited by the rate at which each reactant can be filled into and emptied from the growth chamber (or the lower portion of the recessed structure, whichever is longer).
Electrochemical Deposition (ECD) is a well-established technique for coating surfaces and for filling deep features. This technique is commonly used to produce bottom-up growth of copper in trenches on ULSI circuits: differential plating kinetics are used to obtain “superconformal” or “super-filled” features. (See, P. M. Vereecken, R. A. Binstead, H. Deligianni, P. C. Andricacos, IBM J. Res. Dev. 49 (2005) 3). The differential plating kinetics are generated by using specific additives that segregate to the trench top or bottom and serve as either leveler (for differential inhibition of growth) or catalyst (for differential acceleration of growth). The net effect of ECD methods is a higher growth rate at the trench bottom.
Bottom-up copper CVD extends the idea in electrochemical deposition to CVD approaches. In copper CVD from hexafluoroacetylacetonate-copper-vinyltrimethylsilane, iodine is added as a catalytic-surfactant to enable a bottom-up fill. (See, K. C. Shim, H. B. Lee, O. K. Kwon, H. S. Park, W. Koh, S. W. Kang, J. Electrochem. Soc. 149 (2002) G109). In this method, iodine is provided as a growth promoter and has a concentration that rises inside the feature as the deposition proceeds.
Bottom-up growth was reported by Heitzinger et al. in the specific system of polysilicon deposition from silane (the CVD precursor) when arsine was added to the process gas. (See, C. Heitzinger, W. Pyka, N. Tamaoki, T. Takase, T. Ohmine, S. Selberherr, IEEE Tran. Comput. Aided. Design. 22 (2003) 285.). In this method, arsine acts as a growth suppressor and is also incorporated into the deposition layer. A high process temperature (700° C.) is required to ensure a high reaction rate for arsine. The authors modeled their trench coverage on the basis of depleting arsine concentration in the trench and conclude that the experimental conditions employed result in operation in the time limit domain. (See, page 291, paragraph 3). The time limit stems from the fact that the suppressor is re-emitted from the film surface at some rate and ultimately will diffuse to the bottom of the trench, despite the fact that it has a higher net sticking coefficient and lower concentration with respect to the precursor. In the time limit domain, the bottom-up growth only takes place before the suppressor arrives at the bottom of the via by diffusion. After that, the suppressor concentration saturates from top to bottom and yields equal growth rates at all locations inside the via. A significant disadvantage of the time domain techniques described in Heitzinger et al. is that coating/filling larger structures requires a longer time to build up the appropriate layer thickness; and, thus, the time-limit bottom-up growth will not work because the suppressor will reach the, bottom of the via before the structure is filled. Moreover, the time delay in these systems is very short (e.g. 54.25 s in FIGS. 8 and 23.92 s in FIG. 9 of Heitzinger et al.) and it is difficult to control such a short growth time during processing.
U.S. Pat. No. 7,592,254 discloses deposition techniques using a suppressor gas to generate a conformal or superconformal layer on a recessed feature. In some techniques of this reference, for example, a recessed feature is contacted with a flow of a deposition gas and a flow of a suppressor gas capable of accommodation on the surfaces of the recessed feature in a manner establishing a substantially steady state, anisotropic spatial distribution of the flux suppressor gas to the recessed feature. The flux of suppressor gas to the recessed feature generates suppressor on selected, localized regions of the surfaces of the recessed feature where suppression of the rate of deposition from the deposition gas is desired. U.S. Pat. No. 7,592,254 discloses processes useful for providing superconformal or bottom-up filling of recessed features, wherein the composition and flow rate of suppressor gas is selected such that the rate of deposition onto regions of the recessed feature proximate to (e.g. within about the upper one-third of the feature undergoing processing) the opening and/or in line-of-sight of a source of deposition gas is reduced. This reference further discloses processing wherein deposition preferentially occurs on the side surfaces of the recessed feature proximate to the bottom (e.g. below about the upper one-third of the feature undergoing processing), thereby allowing preferential deposition and growth of a conformal or superconformal layer onto the lower regions of the recessed feature. In some embodiments, for example, the suppressor gas is not desorbed in a form that is capable of subsequent re-accommodation on surfaces, so that it does not diffuse deeper into a high aspect ratio structure.
It will be appreciated from the foregoing that there is currently a need in the art for methods for making smooth thin film structures, including ultrathin smooth conformal films. In addition, methods are needed to enhance the smoothness of thin films for coating and filling recessed features, for example, in nanosized or microsized recessed features of a device substrate.